IEEE Journal of Solid-State Circuits · 1998 · 28 citations · 0 references
EngineeringComputer EngineeringElectrical EngineeringDigital CommunicationMicroelectronicsWireless CommunicationsCmos Circuit DesignCommunication SystemsMixed-signal Integrated Circuit DesignMixed-signal IntegrationNetwork-on-chip DesignRadio-frequency Integrated CircuitsAdaptive EqualizationBaseline Wander CorrectionCmos Analog Integrated CircuitsEqualizationEthernetGigabit EthernetTransceiver ArchitecturesTransceiver Design
A CMOS IC that implements the 802.3 Ethernet standards for 10- and 100-Mb/s data rates is described. The circuit uses mixed-signal techniques to perform transmit pulse shaping, receive adaptive line equalization, baseline wander compensation, and timing recovery. The IC occupies 23 mm/sup 2/ in a 0.6-/spl mu/m single-poly CMOS process and dissipates 850 mW from a 5-V supply.