Low Power and High Speed Optimized 4-bit Array Multiplier Using MOD-GDI Technique

Abstract

Multipliers are the most commonly used elements in today's digital devices. In order to achieve high data throughput in digital signal processing systems, hardware multiplication is the important factor. Depending on the applications which are emerging with the electronics devices, various types of multipliers are emerged. Among all the multipliers, the basic multiplier is Array Multiplier. This paper aims at design of an optimized, low power and high speed 4- bit array multiplier by proposing Modified Gate Diffusion Input (MOD-GDI) technique. With this technique the total propagation delay, power dissipation, and no. of transistors required to design are much more decreased than compared to the Gate Diffusion Input (GDI) and CMOS techniques. Simulations are carried out on mentor graphics tools with 90nm Process technology.