23.5 A 4Gb LPDDR2 STT-MRAM with compact 9F2 1T1MTJ cell and hierarchical bitline architecture

Abstract

Spin-transfer torque magnetic RAM (STT-MRAM) is one of the most promising nonvolatile memories with guaranteed high-speed read and write operations. Along with performance improvements in the tunnel magnetoresistance (TMR) and the magnetic tunnel junction's (MTJ) required switching current, there have also been reports on high-capacity (up to tens of Mb) STT-MRAM [1-4]. In [2] a perpendicular-TMR (pMTJ) device is used to reduce the switching current and a high-speed current sense amplifier is proposed. In [3] a 54nm 2T-1MTJ 14F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> -cell is proposed that uses a high-density DRAM process: self-aligned contact and plug process. However, the unit cell area of STT-MRAM is still much larger than that of DRAM, making STT-MRAM not cost-competitive to contemporary DRAM.