High bandwidth interconnect design opportunities in 2.5D Through-Silicon interposer (TSI)

Abstract

Silicon interposer technology enables the integration of multiple silicon dies on it providing fine pitch interconnects for die-to-die communication and Through-Silicon Vias (TSVs) for package/PCB level connections. Therefore, this technology has been identified as a viable solution for logic and memory types of applications where higher bandwidth in required. In the paper, we characterize thick (t=3μm; w/s=3μm/3μm) as well as thin (t=1μm; w/s=2μm/2μm) front side die-to-die Cu interconnects along with chip-to-substrate interconnects containing Through-Silicon Vias (TSVs) and estimate the data transfer capabilities of them. Evaluation of digital signal interconnect performance shows that the maximum bandwidth requirements expected by the latest memory technologies can be achieved by the silicon interposer technologies characterised in this paper.