A Novel Tunnel FET Design Through Adaptive Bandgap Engineering With Constant Sub-Threshold Slope Over 5 Decades of Current and High $\text{I}_{\mathrm {ON}}/\text{I}_{\mathrm {OFF}}$ Ratio

Abstract

In this letter, a novel hetero-stacked TFET (HS-TFET) is experimentally demonstrated and optimized for the first time, which can effectively suppress the subthreshold slope (SS) degradation without leakage current increase through self-adaptively current replenishing with bandgap engineering, greatly alleviating the critical issue of high average SS in conventional TFETs. Based on CMOS-compatible technology, the fabricated HS-TFETs of vertically stacked Si-Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> source can experimentally achieve superior performance with nearly constant SS over five decades of drain current, high Ion (~14μA/μm @ VDS = -1 V), and large I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> ratio (~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> ). The proposed device with high process compatibility shows great potentials for future ultra-low power applications.