2016 · 19 citations · 7 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesCmos Circuit DesignDynamic Power ReductionLow-power Digital Circuit DesignMixed-signal Integrated Circuit DesignMixed-signal IntegrationTiming AnalysisAnalog-to-digital Converter DesignCmos Logic DesignCmos ScalingCompletion DetectionDynamic Power DissipationOffset Detection
This paper proposes a fine-time-resolution pulse-shrinking (PS) time-to-digital converter (TDC) based on an offset pulse width detection scheme. The proposed PS TDC detects the end of the conversion utilizing a built-in offset pulse unlike the conventional PS TDCs. Thus it prevents an undesirable non-uniform shrinking rate issue in the conventional ones and contributes to fine-resolution, small-area, power-efficient and low-jitter implementation. The prototype TDC fabricated in a 0.18μm standard CMOS technology realizes 9 bit, 1.8 ps sub-gate-delay resolution with 0.07 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area, and achieves 2.16 ps single-shot precision. Its power dissipation is 3.4 mW at 4.4 MS/s.
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Bojan Marković, Simone Tisa, Federica Villa et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 2013 · 173 citations · Full text
Engineering, Computer Engineering, Electrical Engineering +17