Gate-all-around junctionless silicon transistors with atomically thin nanosheet channel (0.65 nm) and record sub-threshold slope (43 mV/dec)

Abstract

A silicon junctionless (JL) trench gate-all-around (GAA) nanowire field-effect transistor with an atomically thin channel thickness of 0.65 nm and a very thin oxide with a thickness of 12.3 nm are demonstrated experimentally. Experimental results indicate that this device with a channel thickness of 0.65 nm achieves a sub-threshold slope (SS) of 43 mV/decade, which is the best yet achieved by any reported JLFET. Owing to the atomically thin channel, this device has an extremely high ION/IOFF current ratio of >108. Furthermore, the atomically thin channel GAA JLFET exhibits a low threshold voltage (VTH) variation and negligible drain-induced barrier lowering (DIBL < 0.4 mV/V). The reported device with the thinnest channel has a very high band-to-band tunneling generation rate of 1.2 × 1024/cm2 s when the channel is scaled down to <1 nm, as confirmed by using the 3D quantum transport simulation tool. This quantum tunneling provides a means of achieving an SS value much lower than its fundamental physical limit.