Floating Gate Nonvolatile Memory Using Individually Cladded Monodispersed Quantum Dots

Abstract

This paper presents nonvolatile memory characteristics of a quantum dot gate floating gate nonvolatile memory (QDNVM) that employs SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> -cladded silicon quantum dots as discrete charge storage nodes of the floating gate. The cladding of Si quantum dots and control of their size are shown to result in a faster access and improved retention time. The floating gate is formed by site-specific self-assembly of SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> -Si quantum dots on the tunnel oxide layer over the p-region between source and drain of an n-channel field-effect transistor (FET). Experimental data on fabricated long channel devices show threshold voltage shift as a function of duration and magnitude of the electrical stress applied during the “Write” operation. Current-voltage characteristics (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> -V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> -V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ) are presented before and after stress. The electrical characteristics are explained using a quantum dot gate FET model which includes the threshold voltage shift (ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> ) as a function of charge on the floating gate quantum dots due to applied electrical stress.