Novel security strategies for SRAM in powered-off state to resist physical attack

Abstract

This paper presents two security strategies for resisting physical attack utilizing data remanence of SRAM in powered-off state. Secure circuits including power supply, power supply selector, powered-off detector, and erase or rewrite circuit are integrated into conventional SRAM to realize erase or rewrite operations and avoid being disassembled by attackers. Implemented with 0.25µm HHNEC CMOS technology, two SRAMs exploiting different strategies show data remanence is successfully eliminated or altered with only 4% and 5% power increased respectively.