65nm cmos technology for low power applications

Abstract

This paper presents a 65nm low power technology offering a dual gate oxide process, multiple Vt devices at a nominal operating voltage of 1.2V, a nine level hierarchical Cu interconnect back-end of line process with low k dielectrics and 0.676mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 0.54mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> SRAM cells, optimized for performance and density, respectively. The key focus of this technology has been low cost, process simplicity and power reduction. A gate dielectric with an nfet leakage current as low as 15pA/mum and with exceptional reliability characteristics has been demonstrated. Moreover, competitive drive current has been achieved, 725/343muA/mum at an off current of 7nA/mum for n/pfets at nominal voltage. A pfet performance enhancement of an additional 13% at 7nA/mum off current was achieved by using mobility enhancement techniques without adding process complexity. An optimized NiSi process and high angle, low dose halo implants contribute to the reduced junction leakage and GIDL current