45-nm gate length CMOS technology and beyond using steep halo

Abstract

45-nm CMOS devices with a steep halo using a high-ramp-rate spike annealing (HRR-SA) are demonstrated with drive currents of 697 and 292 /spl mu/A//spl mu/m for an off current less than 10 nA//spl mu/m at 1.2 V. For an off current less than 300 nA//spl mu/m, 33-nm pMOSFETs have a high drive current of 403 /spl mu/A//spl mu/m at 1.2 V. In order to fabricate a steeper halo than these MOSFETs, a source/drain extension (SDE) activation using the HRR-SA process was performed after a deep source/drain (S/D) formation. By using this sequence defined as a reverse-order S/D formation, 24-nm nMOSFETs are achieved with a high drive current of 796 /spl mu/A//spl mu/m for an off current less than 300 nA//spl mu/m at 1.2 V.