70 nm MOSFET with ultra-shallow, abrupt, and super-doped S/D extension implemented by laser thermal process (LTP)

Abstract

For the first time, a sub-100 nm gate length CMOS transistor is demonstrated with the source/drain extension implemented by laser thermal process (LTP). Ultra-shallow (<30 nm), abrupt, and highly-doped n/sup +/ and p/sup +/ junctions are formed by low-keV implant and 308 nm XeCl excimer laser anneal. Locally selective melting and recrystallization of silicon under the laser beam results in excellent dopant activation for both As and BF/sub 2/. The impact of the laser anneal process is investigated experimentally for MOS transistor characteristics, poly-depletion effect, channel mobility, poly-Si gate and active junction sheet resistances, silicidation, gate oxide leakage, and junction leakage.