A high performance 1.8 V, 0.20 μm CMOS technology with copper metallization

Abstract

A high performance 0.20 /spl mu/m logic technology has been developed with six levels of planarized copper interconnects. 0.15 /spl mu/m transistors (L/sub gate/=0.15/spl plusmn/0.04 /spl mu/m) are optimized for 1.8 V operation to provide high performance with low power-delay products and excellent reliability. Copper has been integrated into the back-end to provide low resistance interconnects. Critical layer pitches for the technology are summarized and enable fabrication of 7.6 /spl mu/m/sup 2/ 6T SRAM cells.