2002 · 101 citations · 0 references
High Performance 0.20EngineeringVlsi DesignComputer ArchitectureμM Cmos TechnologyHigh PerformanceInterconnect (Integrated Circuits)Advanced Packaging (Semiconductors)NanoelectronicsCmos TechnologyElectronic PackagingMaterials EngineeringElectrical EngineeringHigh Performance 1.8Computer EngineeringCritical Layer PitchesMicroelectronicsCopper MetallizationLow-power ElectronicsVlsi ArchitectureApplied PhysicsBeyond Cmos
A high performance 0.20 /spl mu/m logic technology has been developed with six levels of planarized copper interconnects. 0.15 /spl mu/m transistors (L/sub gate/=0.15/spl plusmn/0.04 /spl mu/m) are optimized for 1.8 V operation to provide high performance with low power-delay products and excellent reliability. Copper has been integrated into the back-end to provide low resistance interconnects. Critical layer pitches for the technology are summarized and enable fabrication of 7.6 /spl mu/m/sup 2/ 6T SRAM cells.