Pass transistor designs using pocket implant to improve manufacturability for 256 Mbit DRAM and beyond

Abstract

Pass transistor designs for scaled 256 Mbit DRAM are studied in this paper. It is shown, for the first time, that a L/sub g/=0.25 /spl mu/m and t/sub ox/=85 /spl Aring/ transistor utilizing a pocket implant together with a light V/sub TN/ implant (pocket-with-V/sub TN/) can satisfy the stringent requirements of subthreshold leakage, diode leakage, V/sub T/ during charging, and a tolerance for L/sub g/ variation of 0.08 /spl mu/m for manufacturability. The success of the pocket-implant device in meeting the above design spec is due to the reduced V/sub T/ roll-off at shorter L/sub g/ and reduced body effect at longer L/sub g/ compared to those of a conventional device. An optimum range of substrate bias is determined to be -1.5 to -2 V. It is also shown that the pocket implant does not degrade the gate oxide integrity nor channel hot-electron reliability.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>