Undoped-emitter InP/InGaAs HBTs for high-speed and low-power applications

Abstract

Scaling down the lateral emitter dimension is an effective way to reduce the power dissipation of HBT ICs. Various authors have demonstrated submicrometer HBTs operating at >100 GHz with submilliampere current. On the other hand, there have been few reports on vertical layer structures optimized for low-current operation. At low current, the dominant delay time of HBTs is the emitter charging time. Thus, it is essential to reduce the emitter junction capacitance by increasing the thickness of the emitter depletion layer. In this paper, we propose an undoped-emitter structure for InP-based HBTs and investigate its impact on low-power applications.