CMOS technology scaling for low voltage low power applications

Abstract

This paper reports the scaling guidelines for CMOS technologies optimized for supply voltages lower than standard values in low power applications. The optimum device structures for several lithographic generations targeted for common supply voltages are provided, using an analytical simulator/optimizer incorporating appropriate physically based models. It is shown that lowering the power consumption without significant performance loss is possible. The advantages of scaling the threshold voltage with supply voltage are emphasized.