1G DRAM cell with diagonal bit-line (DBL) configuration and edge operation MOS (EOS) FET

Abstract

In this paper a new capacitor-over-bit line (COB) cell for 1G DRAM is proposed. The cell area of 0.375 /spl mu/m/sup 2/ was obtained with diagonal bit line (DBL) configuration. An edge operation MOS (EOS) transfer gate has been developed which provides SOI-like small S-factor and V/sub TH/-V/sub SUB/ dependence. A storage capacitance of 28.5 fF was achieved with a Ta/sub 2/O/sub 5/ dielectric film on a hemispherical grain Si (HSG) cylinder structure.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>