Understanding soft and hard breakdown statistics, prevalence ratios and energy dissipation during breakdown runaway

Abstract

Since some MOS digital circuits could remain functional after gate oxide breakdown (BD) provided that the post-BD resistance is high enough (1), the separate consideration of soft (SBD) and hard (HBD) breakdown events is necessary to set up an adequate application-specific reliability assessment methodology. In this work we deal with two relevant issues related to this problem. First, we study the statistics of SBD and HBD and their relation to the first-event BD statistical distribution as a function of their prevalence ratios. Second, we consider the modeling of the BD runaway as a means to determine these prevalence ratios as a function of stress conditions and device geometry.