2002 · 33 citations · 0 references
EngineeringElectrical EngineeringMicroelectronicsMicrowave EngineeringSemiconductor DevicesCmos Circuit DesignHigh-frequency Semiconductor DevicesIntegrated Circuit DesignLow-noise Circuit DesignMicrowave Integrated CircuitsRadio-frequency Integrated CircuitsCmos Radio-frequency CircuitsEffective ResistanceLayout Techniques For Noise ReductionLow-noise DesignMicrowave Integrated Circuit DesignNoise FigureRadio-frequency Integrated Circuit DesignRf Cmos Design
We demonstrate that by careful layout optimisation, particularly aimed at reducing the effective gate resistance, a record high maximum oscillation frequency f/sub max/ of 150 GHz can be obtained for an industrial 0.18 /spl mu/m CMOS process showing a cut-off frequency f/sub T/ of 70 GHz. A very low minimum noise figure and good suppression of the substrate noise using a guard-ring is also shown.