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High performance 50 nm CMOS devices for microprocessor and embedded processor core applications
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2002
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Processor Core ApplicationsEngineeringVlsi DesignComputer ArchitecturePower Electronics193-Nm LithographyNm Cmos DevicesNm Cmos TransistorsSemiconductor DeviceNanoelectronicsElectronic CircuitElectrical EngineeringHigh Performance 50Bias Temperature InstabilityComputer EngineeringMicroelectronicsLow-power ElectronicsSystem On ChipEdge 100
50 nm CMOS transistors for high performance and low active power applications are presented. Good short-channel effect control is achieved down to 35 nm gate length. These transistors will be incorporated in a leading edge 100 nm technology, with optimized triple well, nitrided oxide gate dielectrics, 193-nm lithography, 9-level hierarchical Cu interconnects, and low-k dielectrics. These high performance transistors have the best current drive at a given leakage current reported in the literature.