Concepedia

Abstract

This paper introduces a new experimental approach allowing to investigate the recoverable and permanent components in commercial p-channel power VDMOSFETs subjected to negative bias temperature (NBT) stressing. In many applications, devices can be used in multiple modes, which include application of static or pulsed gate voltages at different stages of device operation. Accordingly, we have investigated stress-induced degradation in the cases where the static stress was followed by the pulsed NBT stress conditions and vice versa. The results are discussed in terms of the mechanisms responsible for the buildup of oxide charge and interface traps. It has been shown that the differences in the permanent components of the oxide charge and interface traps between devices exposed to static stress followed by pulsed NBT stress and those exposed only to static NBT stress tend to decrease during the pulsed stress as the duty cycle increases but cannot be completely removed.

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