Signal and Power Integrity Analysis on Integrated Fan-Out PoP (InFO_PoP) Technology for Next Generation Mobile Applications

Abstract

A novel integrated fan-out package on package (InFO_PoP) technology for application processor (AP), memory, and PMIC system is developed for next generation high performance mobile applications. For AP and memory system, the InFO_PoP technology can provide better system performance and lower package profile, compared to current flip-chip package on package (FC_PoP) technology. For signal integrity, the eye height of eye diagram for the InFO_PoP is 24% larger than that for the FC_PoP at LPDDR4. For power integrity, the PDN impedance for the InFO_PoP is 84% lower than that for the FC_PoP at high frequency because of thinner dielectric layer between power/ground planes and shorter path from AP pad to PCB. For AP and PMIC system, an advanced power delivery network (PDN) is proposed to minimize the supply voltage variation and transient time using face-to-face interconnection between AP package and partitioned voltage regulators (PVRs) chip from PMIC package. The voltage variation of the InFO_PoP with PVRs system is 43% lower than that of the FC_PoP with PVRs system. Meanwhile, the InFO_PoP with PVRs system exhibits immediate transient response. The transient time of InFO_PoP with PVRs system is 54% less than that of the FC_PoP with PVRs system.