Chip-level CMOS co-integration of ReRAM-based non-volatile memories

Abstract

This work reports a technique to fabricate ReRAM crossbar arrays co-integrated with fully finished 180nm CMOS technology chips. The proposed integration method enables low-cost ReRAM-CMOS integration and allows the rapid prototyping of complete memory systems. We propose to use W plugs, already present as vias in CMOS technology, as the ReRAM bottom electrodes. The resistance switching layer, WO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> , is obtained by the mask-free rapid thermal oxidation of the W plug surface. With this method, we are able to fabricate 280nm non-volatile memory devices without any additional high-resolution lithography. The integrated memory devices operate at 300 μA, with a high resistance state of 0.6MΩ and low resistance state of 4 kΩ. The electrical characteristics confirm the possibility to integrated non-volatile memories on the back-end-of-the-line of standard CMOS chips, enabling low-cost integration of the memory components with the CMOS driving circuitry.