A novel SIMD architecture for the cell heterogeneous chip-multiprocessor

Abstract

This article consists of a collection of slides from the author's conference presentation. Some of the conclusions of this presentation include: Single chip heterogeneous multicore system takes chip performance to a new level by: 1. exploiting thread level parallelism, 2. exploiting instruction level parallelism, 3. exploiting data level parallelism; Novel pervasive vector-centric architecture; SPE compute engine offers high compute density; Cell delivers unprecedented supercomputer power for consumer applications.