Thread-based Parallelism
Thread-Based Parallelism is a form of shared-memory parallelism in which concurrent execution is achieved through multiple threads of control within a single process, each independently executing instructions but sharing the same memory space to enable efficient data access and communication.
328
Publications
18.4K
Citations
914
Authors
234
Institutions
Publications per year
2017–2026
44
Parents
328
Data speculation support for a chip multiprocessor
Lance Hammond, Mark Willey, Kunle Olukotun · 1998 · 420 citations
Simultaneous multithreading: a platform for next-generation processors
Susan J. Eggers, Joel Emer, Henry M. Levy et al. · IEEE Micro · 1997 · 407 citations
Synergistic Processing in Cell's Multicore Architecture
Michael Gschwind, H. Peter Hofstee, B. Flachs et al. · IEEE Micro · 2006 · 406 citations
IBM power5 chip: a dual-core multithreaded processor
R. Kalla, Balaram Sinharoy, Joel M. Tendler · IEEE Micro · 2004 · 366 citations
1–5 of 328
914
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234
Intel (United States)
Santa Clara, United States
24 h-index
125 publications
6.2K citations
University of Michigan
Ann Arbor, United States
13 h-index
43 publications
2.5K citations
University of California San Diego
San Diego, United States
13 h-index
26 publications
4.5K citations
Universitat Politècnica de Catalunya
Barcelona, Spain
12 h-index
56 publications
3.7K citations
Stanford University
Stanford, United States
10 h-index
32 publications
2.9K citations
Hewlett-Packard (United States)
Palo Alto, United States
9 h-index
20 publications
3.9K citations
Massachusetts Institute of Technology
Cambridge, United States
8 h-index
27 publications
2K citations
Yonsei University
Seoul, South Korea
7 h-index
16 publications
678 citations
1–8 of 234
TPDS · 11 publications · 485 citations
12
h-index
12 publications · 997 citations
11
h-index
7 publications · 295 citations
7
h-index
4 publications · 59 citations
4
h-index
4 publications · 118 citations
4
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1–5