IEEE Micro · 2004 · 366 citations · 8 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureParallel ComputingVirtualizationMemory Subsystem DesignMulticore Processor DesignParallel ArchitecturesParallel Computer ArchitectureParallel Computing SystemsProcessor Core DesignCache DesignCache Hierarchy DesignLow-power MicroarchitectureLow-power Processor DesignMulticore Processor IntegrationThread ParallelismThread-based ParallelismThread-level Parallelism
IBM introduced Power4-based systems in 2001, and the Power5, the next‑generation dual‑core chip, builds on that design to provide natural thread‑level parallelism at the chip level. The Power5 was designed to preserve binary and structural compatibility with Power4 while boosting performance and enhancing server virtualization, reliability, availability, and serviceability, and the paper outlines the approach to improve chip‑level performance. The Power5 builds on the Power4 architecture by integrating two cores, a shared second‑level cache, a directory for an off‑chip third‑level cache, and inter‑chip circuitry, while also incorporating enhancements for performance, virtualization, reliability, availability, and serviceability.
IBM introduced Power4-based systems in 2001. The Power4 design integrates two processor cores on a single chip, a shared second-level cache, a directory for an off-chip third-level cache, and the necessary circuitry to connect it to other Power4 chips to form a system. The dual-processor chip provides natural thread-level parallelism at the chip level. The Power5 is the next-generation chip in this line. One of our key goals in designing the Power5 was to maintain both binary and structural compatibility with existing Power4 systems to ensure that binaries continue executing properly and all application optimizations carry forward to newer systems. With that base requirement, we specified increased performance and other functional enhancements of server virtualization, reliability, availability, and serviceability at both chip and system levels. We describe the approach we used to improve chip-level performance.
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