Back Illuminated Vertically Pinned Photodiode with in Depth Charge Storage

Abstract

A novel 1.4µm pitch pixel architecture dedicated for backside process with embedded vertically pinned photodiode is investigated. The proof of a vertical pinning is made thanks to a study of the maximum diode depletion potential for different diode widths. Diode doping strategy is described in order to optimize in-depth charge storage. Simulation results show good matching when compared to scanning capacitance microscopy (SCM). A new silicon on insulator (SOI) wafer with embedded ONO broadband antireflective coating (ARC) fabrication technique is presented and demonstrates further improvement in terms of quantum efficiency (QE), with 63% in green spectrum. Process solutions such as additional thermal treatment are provided to control maximum diode depletion potential. A transfer gate (TG) is stacked above the photodiode and its according charge transfer technique is investigated. Pixel performances show full-well capacity of more than 11000 electrons.