3-D Silicon-on-Insulator Integrated Circuits With NFET and PFET on Separate Layers Using Au/SiO₂Hybrid Bonding

Abstract

We report the first demonstration of 3-D integrated circuits (3-D ICs) through the low-temperature (200 °C) hybrid bonding of 3-μm-diameter gold (Au) contacts embedded in a polished silicon oxide (SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) surface. N-type field-effect transistors (NFETs) and p-type FETs (PFETs) prepared on separate silicon-on-insulator wafers are vertically connected after the completion of the FET process including metal wires. Ultrahigh-density integration is possible because the developed technology requires no additional area for electrical interconnect sites. At the same time, the overall IC performance can be improved because the process and design for the NFETs and PFETs are independently optimized before bonding. The reliability of the hybrid electrical connection is confirmed using a daisy-chain test device of more than 23000 electrodes. Feasibility tests are also performed by developing 3-D-CMOS inverters and 3-D-ring oscillators (ROs) with 101 stages. The experimental results indicate that the developed technology is promising for high-performance 3-D ICs.