Ge-Source Vertical Tunnel FETs Using a Novel Replacement-Source Integration Scheme

Abstract

The Ge-source tunnel FETs (TFETs) are fabricated using a novel replacement-source approach, whereby a dummy source is replaced at the end of the process flow by the final source material to form an heterojunction. We show that the source can be successfully replaced while maintaining the gate dielectric integrity in the gate-source overlap (GS-OL) region and selectively to the exposed materials. Due to the in situ-doped epitaxial-grown source and the low thermal budget, this integration scheme leads to the formation of a highly doped source and an abrupt tunnel heterojunction and allows the integration of complementary devices. Electrical characterization of the devices shows performance improvement over their SiGe-source heterojunction and Si homojunction vertical TFET counterparts. Temperature dependence indicates that the subthreshold region of the devices is degraded due to trap-assisted tunneling (TAT). Band-to-band tunneling (BTBT) contribution is, however, revealed at low temperature (78 K) with a minimum point slope of ~50 mV/decade. The impact on performance of different device parameters is assessed. The amount of GS-OL or crystalline Ge (c-Ge) thickness in the source does not affect the device characteristics owing to the fact that the devices are dominated by point tunneling. On the other hand, the thickness of the gate dielectric as well as the doping profile at the tunnel junction modifies the device performance. The gate-drain underlap is shown to reduce the ambipolar behavior of the devices without affecting their ON-characteristics. Very low variability is measured for the ON-current in the devices where BTBT dominates, while variability increases in the TAT region.