28nm FD-SOI technology and design platform for sub-10pJ/cycle and SER-immune 32bits processors

Abstract

This paper presents the technology and design optimization performed in 28nm FD-SOI to reach ultra-low energy and/or soft-error tolerance on ARM® Cortex®-M4 32bits processors. A 8.9pJ per cycle efficiency was measured while performing at 0.5V/45MHz, and a soft-error immunity was measured under alpha and neutron radiation while performing at 1.0V/730MHz. These results were achieved by the design of specific standard cells, macros and clock tree architectures, the technology intrinsic performances, and an adapted CAD flow.