26.1 A 5.5mW ADPLL-based receiver with hybrid-loop interference rejection for BLE application in 65nm CMOS

Abstract

Various Ultra-Low-Power (ULP) RX architectures [1-4] for Bluetooth™ Low Energy (BLE) have been developed for minimizing the RX power consumption. A PLL-based RX architecture [1] is very attractive to improve the energy efficiency. While the single-channel configuration without multi-bit ADC realizes under 3mW power consumption and over -90dBm sensitivity, the 2nd and 3rd Adjacent Channel Interference Rejections (ACRs) do not meet the BLE requirements. Although the ACR can be improved by inserting high-order LPFs into the regeneration loop, it critically degrades the closed-loop stability. The Sliding IF (SIF) architecture is an alternative approach to overcome the ACR issue with high-energy efficiency. The reported receivers in [2,3] succeed in achieving over 20dB ACR, however, the SIF still has a problem of low out-of-band blocker tolerance because of unwanted signal at the image frequency. An off/on chip bandpass filter inserted at the front of the LNA can reject the image signal, which incurs a signal loss and degrades the energy efficiency of the RX. This paper presents a new PLL-based RX with hybrid loop that achieves over 20dB 2nd/3rd ACR without any external RF filters. The proposed RX employs two key features: (1) the high-interference-tolerance hybrid-loop structure based on an ADPLL, and (2) a novel single-channel receiving method, which enables the conversion of the constellation from FSK to a differential BPSK (DBPSK) signal.