Satoshi Kondo - Concepedia

Concepedia

Author

Satoshi Kondo

Tokyo Institute of Technology ORCID

Also Known As

Kenichi Okada, Satoshi Kondo, 永島典明

33

Publications

1.4K

Citations

17

H-Index

31

Concepts

All Affiliations

Tokyo Institute of Technology Toshiba (Japan)Apple (United States)Advantest (Japan)

SK

About

Satoshi Kondo is an author at Tokyo Institute of Technology specializing in engineering, computer engineering, and electromagnetic compatibility.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	13	14	867
2	Medicine	1	1	240
3	Public Health	1	1	240
4	Applied Physics	1	1	57
5	Biostatistics	1	1	240

Satoshi Kondo

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20

Publications

1.4K

Citations

17

H-Index

	Year	Citations
A New Z Score Curve of the Coronary Arterial Internal Diameter Using the Lambda-Mu-Sigma Method in a Pediatric Population Tohru Kobayashi, Shigeto Fuse, Naoko Sakamoto, Journal of the American Society of Echocardiography Heart FailureCardiovascular DiseasePediatric Heart DiseaseAtherosclerosisCoronary Unit	2016	240
A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique Wei Deng, Dongsheng Yang, Tomohiro Ueno, IEEE Journal of Solid-State Circuits Electrical EngineeringInjection LockingEngineeringAnalog-to-digital ConverterData Converter	2014	148
64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay Rui Wu, Ryo Minami, Yuuki Tsukui, IEEE Journal of Solid-State Circuits Wireless CommunicationsMulti-carrier CommunicationEngineeringRadio FrequencyMicrowave Transmission	2017	130
20.3 A 64-QAM 60GHz CMOS transceiver with 4-channel bonding Kenichi Okada, Ryo Minami, Yuuki Tsukui, EngineeringRadio FrequencyHigh-frequency DeviceMixed-signal Integrated CircuitQuadrature Injection-locked Oscillator	2014	111
A Fractional-<italic>N</italic> Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB Aravind Tharayil Narayanan, Makihiko Katsuragi, Kento Kimura, IEEE Journal of Solid-State Circuits Fractional-n PllIntrinsic JitterSub-sampling Pll-250 DbData Converter	2016	111
A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad Teerachot Siriburanon, Satoshi Kondo, Makihiko Katsuragi, IEEE Journal of Solid-State Circuits Electrical EngineeringEngineeringRadio FrequencyOscillatorsHigh-frequency Device	2016	101
A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance Jian Pang, Shotaro Maki, Seitarou Kawai, IEEE Journal of Solid-State Circuits Ieee 802.11AyEngineeringRadio FrequencyI/q ImbalanceMixed-signal Integrated Circuit	2019	92
A 2.2 GHz -242 dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, IEEE Journal of Solid-State Circuits Voltage-domain DigitizationData ConverterMixed-signal Integrated CircuitAnalog DesignRms Jitter	2016	78
A 20-ch TDC/ADC Hybrid Architecture LiDAR SoC for 240 <inline-formula> <tex-math notation="LaTeX">$\times$ </tex-math> </inline-formula> 96 Pixel 200-m Range Imaging With Smart Accumulation Technique and Residue Quantizing SAR ADC Kentaro Yoshioka, Hiroshi Kubota, Tomonori Fukushima, IEEE Journal of Solid-State Circuits	2018	75
15.1 A 0.0066mm<sup>2</sup> 780&#x03BC;W fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique Wei Deng, Dongsheng Yang, Tomohiro Ueno, Edge-injection TechniqueElectrical EngineeringEngineeringHigh-frequency DeviceClock Recovery	2014	57

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