9.5 A dual-band digital-WiFi 802.11a/b/g/n transmitter SoC with digital I/Q combining and diamond profile mapping for compact die area and improved efficiency in 40nm CMOS

Abstract

Digital transmitters (DTX) have gained interest in the past few years because of their potential to provide compact die area, better efficiency due to the switching nature of the power amplifier core, and scaling with CMOS technology [1–3]. Quadrature DTX architecture [1] is favored over polar [3] or outphasing [4] for wideband applications, such as WiFi, because of its ability to scale easily to higher signal bandwidth. Moreover, there is no need for a CORDIC block to convert I/Q signals to amplitude/phase signals [3], which results in large-signal bandwidth expansion, nor the need for very precise alignment [3,4] using fast digital circuits and excessive calibrations. However, the promised potential of quadrature DTX technology fell short of what has been expected because of the excessive parasitics at the TX output as a result of the traditional way of combining the two I and Q paths at the PA output [1]. An I/Q power-cell sharing method by time-division multiplexing between local oscillator (LO) I/Q signals has been proposed for a low-band cellular DPA (800MHz) to address this problem [2]. However, the technique requires 25% LO, which is very difficult to realize for the 5.5GHz WiFi band and is very power hungry. The DTX in Fig. 9.5.1 addresses this issue through a different method of I and Q combining as well as a new digital baseband signal mapping for a compact die area, low parasitics at the PA output, lower loading on LO lines and better overall efficiency.