Advanced 3D Monolithic hybrid CMOS with Sub-50 nm gate inverters featuring replacement metal gate (RMG)-InGaAs nFETs on SiGe-OI Fin pFETs

Abstract

We demonstrate, for the first time, scaled hybrid inverters built in a 3D Monolithic (3DM) CMOS process featuring short-channel replacement metal gate (RMG) InGaAs-OI wide-fin/planar nFET top layer and SiGe-OI fin pFET bottom layer. We achieve state-of-the-art device integration, using raised source drain (RSD) on both levels and silicide on bottom pFETs. Bottom SiGe-OI pFETs are scaled down to sub-20 nm gate length (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> ) using a gate first (GF) flow, and top InGaAs nFETs scaled down to sub-50 nm L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> are fabricated using a RMG process. With an optimized thermal budget for the top InGaAs nFETs, we show that the 3D integration scheme does not degrade the performance of the bottom SiGe-OI pFETs. Finally, we demonstrate well-behaved integrated inverters with sub-50 nm L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> down to V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> = 0.25 V.