Hardware SecurityLogic SynthesisNew FamilyEngineeringLogic FamilyDynamic LogicFormal MethodsComputer EngineeringComputer ArchitectureSystems EngineeringHardware Description LanguageComputer ScienceSynchronization ClockDigital Circuit DesignParallel ComputingFormal VerificationMemory ArchitectureData Modeling
In this paper a new family of low-power dynamic logic called Data-Driven Dynamic Logic (D3L) is introduced. In this logic family, the synchronization clock has been eliminated, and correct sequencing is maintained by appropriate use of data instances. Then, it is shown that replacement of the clock with input data implies less power dissipation without speed degradation compared to conventional dynamic logic.
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