An 11-bit 45MS/s pipelined ADC with rapid calibration of DAC errors in a multi-bit pipeline stage

Abstract

A technique to rapidly correct for DAC errors in the multi-bit first stage of an 11-bit pipelined ADC is presented. Using a split-ADC approach the digital background scheme is validated with a proof-of-concept prototype fabricated in 1.8 V 0.18 mum CMOS, where the calibration scheme improves the INL of the ADC at f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> =45 MS/s, from +6.1/-6.4 LSB to +1.1/-1 LSB after calibration. The SNDR/SFDR is improved from 46.9 dB/48.9 dB to 60.1 dB/70 dB after calibration. Calibration is achieved in ~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> clock cycles.