A 60GHz power amplifier with 14.5dBm saturation power and 25% peak PAE in CMOS 65nm SOI

Abstract

A 60 GHz wideband power amplifier (PA) is fabricated in standard CMOS SOI 65 nm process. The PA is constituted by two cascode stages. Input, output and inter-stage matching use coplanar wave guide (CPW) transmission lines that have low losses thanks to the high resistivity SOI substrate. The PA measurements are carried out for supply voltages V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> going from 1.2 V to 2.6 V and achieve a saturation power of 10 dBm to 16.5 dBm respectively. The peak power added efficiency is higher than 20% for all applied V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> values.