A 3.5 GHz Digital Fractional-N PLL Frequency Synthesizer Based on Ring Oscillator Frequency-to-Digital Conversion

Abstract

A 3.5 GHz digital fractional-N PLL in 65 nm CMOS technology is presented that achieves phase noise and spurious tone performance comparable to those of a high-performance analog PLL. It is enabled by a new second-order frequency-to-digital converter that uses a dual-mode ring oscillator and digital logic instead of a charge pump and ADC. It also incorporates a new technique to reduce excess phase noise that would otherwise be caused by component mismatches when the DCO input is near integer boundaries. The PLL's largest in-band fractional spur is -60 dBc, its worst-case reference spur is -81 dBc, and its phase noise is -93, -126, and -151 dBc/Hz at offsets of 100 kHz, 1 MHz, and 20 MHz, respectively. Its active area is 0.34 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and it dissipates 15.6 mW from a 1 V supply.