Hot-carrier effects and lifetime prediction in off-state operation of deep submicron SOI N-MOSFETs

Abstract

Hot-carrier effects (HCE) induced by the parasitic bipolar transistor (PBT) action are thoroughly investigated in deep submicron N-channel SOI MOSFETs for a wide range of temperature and gate length. A multistage device degradation is highlighted for all the experimental conditions. Original V/sub t/ variations are also obtained for short-channel devices, a reduction of the threshold voltage being observed for intermediate values of stress time in the case of high stress drain biases. At low temperature (LT), an improvement of the device aging can be obtained in the low V/sub d/ range because of the significant reduction of the leakage current in the PBT regime. However, in the case of high V/sub d/, since the strong leakage current cannot be suppressed at LT, the device aging is larger than that obtained at room temperature. On the other hand, the device lifetime in off-state operation is carefully predicted as a function of gate length with various methods. Numerical simulations are also used in order to propose optimized silicon-on-insulator (SOI) architectures for alleviating the PBT action and improving the device performance and reliability.