1987 · 32 citations · 0 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignBipolar Junction TransistorsCmos Circuit DesignIntegrated Circuit DesignMetal-oxide-semiconductor Field-effect TransistorsTiming AnalysisBipolar TechnologyHigh-speed Cmos DesignPolysiliconSelf-aligned Structures
A sophisticated bipolar technology for high speed and low power dissipation VLSI's has been developed. It employs an Emitter-base Self-aligned structure with Polysilicon Electrodes and Resistors (ESPER) combined with U-FOX (U-groove isolation with thick Field OXide). An ECL circuit with a minimum gate delay time of 38.8 ps has been obtained at a switching current (I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CS</inf> ) of 1.28 mA. At the same time, we have fabricated low power type transistors. In this circuit, we have obtained a minimum gate delay time of 60.2 ps at I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CS</inf> of 0.34 mA and a wiring length effect of 50 ps/mm for a 0.32 mA emitter follower current. This new process is advantageous to high performance VISI's and giga-digital systems.