A 40nm 7Gb/s/pin single-ended transceiver with jitter and ISI reduction techniques for high-speed DRAM interface

Abstract

A 7Gb/s single ended transceiver with low jitter and ISI is implemented in 40 nm DRAM process. DRAM optimized LC PLL achieves inductor Q of 3.86 and results in random jitter of 670 fs RMS. A clock tree regulator with closed loop replica path reduces low as well as high frequency noise. RX 2-tap hybrid DFE combining sampling and integration methods reduces power and area by 37% and 24%, compared to the integrating DFE. Moreover, on-chip de-emphasis circuit in TX multiplexer reduces ISI of both on and off chip.