IEEE Journal of Solid-State Circuits · 2001 · 32 citations · 11 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsPackaging DesignSemiconductor DevicesChip PackagingDevice ReliabilityMemory DevicesMemory Subsystem DesignDie ArchitectureFlip-chip PackagingLow-noise DesignMemory Built-in Self-repairNon-volatile Memory DesignOn-chip Memory DesignPackaging Reliability TestingPackaging-induced Reliability
A multigigabit DRAM technology was developed that features a low-noise 6F/sup 2/ open-bitline cell with fully utilized edge arrays, distributed overdriven sensing for operation below 1 V, and a highly reliable post-packaging repair scheme using a stacked-flash fuse. This technology, which can be used to fabricate a 0,13-/spl mu/m 180-mm/sup 2/ 1-Gb DRAM assembled in a 400-mil package, was verified using a 57.6-mm/sup 2/, 200-MHz array-cycle, 256-Mb test chip with 0.109-/spl mu/m/sup 2/ cells.
11
Restle, Park, Lloyd · 1992 · 109 citations
Engineering, Computer Engineering, Electrical Engineering +15
A 5 V-only 64K dynamic RAM based on high S/N design
H. Masuda, R. Hori, Y. Kamigaki et al. · IEEE Journal of Solid-State Circuits · 1980 · 54 citations
Engineering, Computer Engineering, Electrical Engineering +17