Wafer-scale 3D integration of InGaAs image sensors with Si readout circuits

TLDR

The study modifies wafer‑scale 3D integration to hybridize InP‑based image sensor arrays with silicon readout circuits. InGaAs image arrays grown on InP substrates were fabricated alongside silicon‑on‑insulator readout circuits, then the 150‑mm InP wafer was bonded to the SOI wafer and connected to the Si readout circuits through 3D vias. A 1024×1024 diode array with 8‑µm pixels was demonstrated, confirming wafer‑scale 3D integration of a compound semiconductor with silicon.

Abstract

In this work, we modified our wafer-scale 3D integration technique, originally developed for Si, to hybridize InP-based image sensor arrays with Si readout circuits. InGaAs image arrays based on the InGaAs layer grown on InP substrates were fabricated in the same processing line as silicon-on-insulator (SOI) readout circuits. The finished 150-mm-diameter InP wafer was then directly bonded to the SOI wafer and interconnected to the Si readout circuits by 3D vias. A 1024 × 1024 diode array with 8-µm pixel size is demonstrated. This work shows the wafer-scale 3D integration of a compound semiconductor with Si.