Skew reduction in clock trees using wire width optimization

Abstract

A novel technique for designing binary clock trees with reduced delay and near-zero skew is described. Starting with the minimum possible metal pitch for the tree branches, the proposed algorithm increases the width of selected branches using a set of skew reduction heuristics. A technique to deterministically reduce the phase delay by varying the widths of the main branches is also described. The main advantage of the proposed technique is the decoupling of the clock-net routing from the skew reduction phase. This makes it possible to route the clock net taking macro blockages into account, an important need in today's design methodologies. A router which yields a binary-tree route can be used. A simple method to reduce the delay of a clock net arbitarily is also shown. A new criterion in clock net synthesis, i.e., robustness, is also introduced.