Sub-60nm Si tunnel field effect transistors with I<inf>on</inf> >100 µA/µm

Abstract

Si-tunneling field effect transistors (TFETs) with a record I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</inf> >100 µA/µm and high I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</inf> /I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</inf> ratio (> 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> ) at V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</inf> =1V are reported. Using an optimal spike and millisec flash anneal coupled with an engineered source-gate overlap through a gate-last process, Si TFETs have been demonstrated with 10 to 1000 times greater current than previously reported. The devices exhibit negative differential resistance and temperature dependencies consistent with band-to-band tunneling and current characteristics in excellent agreement with 2D TCAD simulations.