Dense heterogeneous integration for InP Bi-CMOS technology

Abstract

InP Bi-CMOS technology capable of wafer-scale device-level heterogeneous integration (HI) of InP HBTs and CMOS has been developed. With this technology, full simultaneous utilization of III-V device speed and CMOS circuit complexity is possible. Simple ICs and test structures have been fabricated, showing no significant CMOS or HBT degradation and high heterogeneous interconnect yield. The heterogeneously integrated differential amplifiers with record performance and HBTs with f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> =400 GHz were obtained. Thermal vias to the Si substrate provide sufficient heat path to lower HI HBT thermal resistances close to on-InP values. Resulting circuits maintain maximum CMOS integration density and HBT performance, while keeping the heterogeneous interconnect length below 5 mum.