IEEE Micro · 1993 · 81 citations · 7 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureHardware-software Co-designMicroelectronicsAccelerator ArchitectureInstruction Set ArchitectureMicroarchitecture DesignProcessor Core DesignProcessor MicroarchitectureSuperscalar ProcessingAddress TranslationCache DesignCache OrganizationCmos ScalingFloating-point ArithmeticFloating-point Unit DesignSuperscalar ExecutionSuperscalar Microarchitecture
The PA7100 CPU, the first precision-architecture, reduced-instruction-set-computer (PA-RISC) architecture implementation to combine an integer core and floating-point coprocessor into a single-chip format, is described. It incorporates superscalar execution and supports clock rates of up to 100 MHz in standard 0.8- mu m CMOS. Features such as a flexible primary cache organization and multiprocessing capability allow the device to be scaled to a variety of system applications, price ranges, and performance levels. The microprocessor instruction execution pipeline, cache design, translation look-aside buffer (TLB) for virtual address translation, floating-point unit, and system interface bus are discussed. The design, test, and verification methods used in the development of the PA7100 are reviewed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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S. Mirapuri, Michael Woodacre, N. Vasseghi · IEEE Micro · 1992 · 74 citations
A high speed superscalar PA-RISC processor
E. DeLano, W. Walker, J. Yetter et al. · 2003 · 28 citations