Continuous deep reactive ion etching of tapered via holes for three-dimensional integration

Abstract

A continuous SF 6 /O 2 plasma process at room temperature has been used to etch tapered through-silicon vias using a DRIE-ICP tool. These features (10-100 m in diameter) are aimed for applications in 3D integration and MEMS packaging. The effects of various process parameters such as O 2 flow rate, platen bias, pressure and substrate temperature on the via profile (depth, slope angle and aspect ratio) development are investigated. The etching mechanism was also studied and x-ray photoelectron spectroscopy (XPS) analysis reveals a SiO x passivation layer of the order of 2 nm on the via sidewall and a substantial temperature dependence. Both tapering and anisotropy of etching depend on this passivation layer formation. Finally, suitable tapered vias with an aspect ratio of 5 and a slope angle of 83 are obtained by properly balancing the etching regimes. In this condition, a maximum etch rate of 7 m min -1 is achieved.