Design methodology for chip-on-chip applications

Abstract

Chip-on-chip is a viable alternative solution for some applications requiring logic and memory integration. However, one of the impediments to this technology is lack of design infrastructure. Conventional multichip design methodologies which are extensions of standard board designs are not well-suited to chip-on-chip designs. To address this issue, we have implemented a chip-on-chip design methodology that incorporates both logic and memory design database and utilizes an auto-router to minimize routing layers. It emulates a two-layer routing system by using a single redistribution metal layer on each chip and solder bumps as vias. In this paper, we describe several chip-on-chip modules designed using this methodology and discuss the method's limitations.