Kazuaki Murakami - Concepedia

Author

Kazuaki Murakami

Kyushu University

Also Known As

K Murakami, K. J. Murakami, K. Murakami, Kazuaki J. MURAKAMI, Kazuaki J. Murakami, Kazuaki Murakami

103

Publications

843

Citations

H-Index

Concepts

All Affiliations

Kyushu University Institute of Systems, Information Technologies and Nanotechnologies Tokyo Electron (Japan)The University of Tokyo

About

Kazuaki Murakami is an author at Kyushu University specializing in engineering, computer science, and computer engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	10	10	295
2	Computer Engineering	9	9	284
3	Computer Science	9	9	284
4	Data Science	1	1	11
5	Electrical Engineering	1	1	11

Kazuaki Murakami

Publications

601

Citations

H-Index

Page 1

	Year	Citations
Way-predicting set-associative cache for high performance and low energy consumption Koji Inoue, Tohru Ishihara, Kazuaki Murakami	1999	296
Optimizing the DRAM refresh count for merged DRAM/logic LSIs Taku Ohsawa, Koji Kai, Kazuaki Murakami Hardware SecurityLogic PortionEngineeringDram Refresh CountHigh-performance Architecture	1998	92
Parallel processing RAM chip with 256 Mb DRAM and quad processors Kazuaki Murakami, Satoru Shirakawa, Hiroshi Miyajima EngineeringComputer ArchitectureHardware ArchitectureMulti-channel Memory ArchitectureHardware Security	2002	51
SIMP (Single Instruction stream/Multiple instruction Pipelining): a novel high-speed single-processor architecture Kazuaki Murakami, Naoki Irie, Shunsuke Tomita Multiple InstructionsEngineeringCompiler TechnologyComputer ArchitectureSoftware Engineering	1989	47
Dynamically variable line-size cache exploiting high on-chip memory bandwidth of merged DRAM/logic LSIs Koji Inoue, Kazuaki Murakami Non-volatile MemoryEngineeringVlsi DesignComputer ArchitectureNovel Cache Architecture	1999	31
Technology mapping technique for throughput enhancement of character projection equipment Makoto Sugihara, Taiga Takata, Kenta Nakamura, Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE Technology Mapping TechniqueEngineeringElectron-beam LithographyElectronic Design AutomationComputer Architecture	2006	15
Task scheduling for reliable cache architectures of multiprocessor systems Makoto Sugihara, Tohru Ishihara, Kazuaki Murakami Design, Automation, and Test in Europe EngineeringComputer ArchitectureProcessor ArchitectureHardware SecurityHigh-performance Architecture	2007	13
Reducing reconfiguration time of reconfigurable computing systems in integrated temporal partitioning and physical design framework Farhad Mehdipour, Morteza Saheb Zamani, HamidReza Ahmadifar, International Parallel and Distributed Processing Symposium EngineeringReconfiguration TimeComputer ArchitectureHardware ArchitecturePhysical Design Framework	2006	12
ALU-array based reconfigurable accelerator for energy efficient executions Koji Inoue, Hamid Noori, Farhad Mehdipour, EngineeringBranch PredictorEmbedded MicroprocessorsHardware AccelerationComputer Engineering	2009	12
A Character Size Optimization Technique for Throughput Enhancement of Character Projection Lithography Makoto Sugihara, Tomoaki Takata, Kenta Nakamura, Electron Beam ShotsElectrical EngineeringPhysical Design (Electronics)EngineeringElectron-beam Lithography	2006	11

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